1. Field of the Invention
This invention relates generally to the field of data processing systems, and more particularly, to interrupts in data processing systems. Specifically, the present invention relates to improving the processing of interrupts.
2. Description of the Related Art
The demand for quicker and more powerful personal computers has led to many technological advances in the computer industry, including the development of faster processors to run software programs. However, at times it is necessary to stop a processor from running a software program to take care of an exceptional condition presented to the processor in the form of an interrupt request. The condition may be from an external hardware device that requires the use of the processor. There may be several types of interrupts and, to handle an interrupt request, the processor invokes an appropriate program depending on the type of interrupt request received.
Interrupt requests are stored in a status register while the processor determines what types of interrupt requests are pending. The status register has generally been designed to either store a single coded interrupt request or to hold many bits each indicating a type of interrupt request. In either case, when multiple interrupt requests are pending hardware logic must be designed to institute a priority mechanism. To institute a more complicated priority mechanism based on all the types of interrupt requests pending and the type of program that was being run in the processor can lead to substantial hardware. This hardware will occupy more area on the integrated circuit chip or require additional space in an implementation with discrete hardware components.
While an interrupt request is processed, the status register is not modified by the hardware preventing any additional interrupt requests from being taken. This leads to interrupt requests being lost. To prevent interrupt requests from being lost, current designs utilize other secondary status registers to hold these interrupt requests. This solution again requires additional hardware. Furthermore, the procedure is time consuming because interrupt handler software has to read the interrupt requests from multiple hardware elements. Thus, this solution exacerbates the problems associated with a single status register implementation.